While studying Udemy course “Digital Electronics & Logic Design Circuits” about 2’s complement and 1’s complement, I got puzzled with why all binary 1 (ex. 1111) is -1 in 2’complement, why positive 0 and negative 0 is same in 2’s complement, and why the range is different for 2’s and 1’s complements. I also had a misunderstanding that a negative number is the positive number with the most significant bit changed to 1, for example, -1 would be 1001.

Later, I learned the purpose of the complement system is mainly to perform subtraction through addition, for instance 7 – 2 is the same as 7 + (-2). It becomes straightforward by first listing positive numbers, and then listing individual negative numbers for 1’s and 2’s complements. I drew the following table with N=4 as an example and everything became clear.

It answers my questions:

• Why 1111 is -1 in 2’s complement
• Why 2’s complement solves the double zero issue
• Why 1’s complement and 2’s complement have different ranges

I often get confused with how NMOS or PMOS transistors output the logic “0” and “1”. One misconception I had is that I thought when NMOS or PMOS is in an “off” state, there should be an output. However, I missed an important fact that for a gate to transmit a clear output, the circuit must be able to conduct between Drain and Source. And it is in this sense that the resistance between D and S, the R_ds, and the Ohm’s Law of electrical circuits helps me understand the case.

For NMOS, when V_gs is positive (as an input of logic “1”), the circuit becomes conductive. As the R_ds becomes very low and essentially pulls the output (Drain) to the voltage close to ground, it transmits a clear logic “0”. When V_gs is zero or negative (as an input of logic “0”), the circuit becomes non-conductive, resulting in a high resistant R_ds. Therefore, the voltage on output (Drain) becomes undefined, depending on the rest of the circuit that D is connected with.

On the other hand, for PMOS, when V_gs is negative (as an input of logic “0”), the circuit becomes conductive. As the R_ds becomes very low and essentially pulls the output (Drain) to the voltage close to V_dd, it transmits a clear logic “1”. When V_gs is zero or positive (as an input of logic “1”), the circuit becomes non-conductive, resulting in a high resistant R_ds. This causes the voltage on output (Drain) to become undefined, which, similar to NMOS, depends on the rest of the circuit that D is connected with.

By combining both PMOS and NMOS together as a CMOS, a clear output (Drain) of “0” or “1” can be transmitted with accordance to the signal from the input (Gate). This can be clearly shown in the NOT gate in the picture below.