The fibonacci sequence is a sequence of numbers where the first two terms are both 1 and the next terms are the sum of the two previous terms. In order to output the terms of this sequence using TL-Verilog, you need to be able to access previous cycles of numbers. This is where the “>>” operation comes in. 

In TL-Verilog, >> indicates that you want the value of some previous cycle of a variable. The storage of values from previous cycle is realized through the “D Flip-Flop“, the square block with a small triangle in it. For example, if you set something equal to >>3$num, the value will be the value of num three cycles before. With this operation in mind, it seems fairly trivial to come up with the code for the fibonacci sequence. The line of code

$num[31:0] = >>1$num + >>2$num;

seems to be enough. What this line means is that the variable “num”s value is equal to the previous cycle’s value and the value two cycles earlier. However, the only issue with this is that for the first cycle, there is no previous cycle. The way to bypass this issue is through a reset variable and a multiplexer.

The reset variable has value 1 for the first couple cycles. Afterwards, the value becomes 0. This works well with a multiplexer, since you could define num as some value when reset is 1 and then start computing the rest of the terms when reset is 0. Since you want the first two terms to be 1, the lines of code will be the following:

$num[31:0] = $reset ? 1 : (>>1$num + >>2$num);

The waveform shows reset lasts more than two cycles (yellow highlighted), enough to get two previous cycles of consecutive “1” as the initial fibonacci sequence.

In order to get familiar with Makerchip platform and TL-Verilog, a pipelined Pythagorean example is given as a tutorial. The tutorial is very helpful, however, reading waveform can be a bit challenging especially when pipelining and the valid signal are combined together. Please read through the “VALIDITY TUTORIAL” from the “Tutorials” page.

Pipelining is an optimization strategy that involves executing parts of different tasks simultaneously. Imagine a program with three different sections. Each section takes the same amount of time to run. In the first cycle, the first part of the first task will receive its input and output it to the second part. In the second cycle, the second part of the first task will perform its job. However, the first part of the second task will also run at the same time. Then, in the third cycle, the third part of the first task will run and output the result. At the same time, the second part of the second task and the first part of the third task will also run. This allows the entire program to run much faster than iterating through each task individually.

The valid signal is composed of two random bits (for the Pythagorean example). This signal will determine if the program will run through a task with a ¼ chance of doing so. The picture below shows that when the valid signal is true (the line is green) the task runs and the numbers are highlighted. When it’s false (the line is blue) the numbers are grayed out. 

However, you may be wondering why the numbers directly above the green line, unless there is a green line before it, are grayed out. This is because of the aforementioned pipelining strategy. The valid signal and the first part of the task aren’t run in the same section. The valid signal is determined first before being given to the first part. Because of this, the task that will actually run is the task in the cycle directly afterwards.

In the above waveform, I highlighted three tasks: task 1 (yellow), task 2 (red), and task 3 (blue). The solid yellow marks the valid cycle that is followed by pipeline 1 (@1) of task 1. The solid red marks the valid cycle that is followed by pipeline 1 of task 2. The solid blue marks the valid cycle that is followed by pipeline 1 of task 3. Note: the validity cycle only marks the initiating of pipeline 1 of a task and won’t prevent running of further pipelines for the same task even if the validity cycle is done. 

ChipCraft is a good course for beginners to learn chip design. I found it is compelling to break down some of its 300+ slides and hopefully it may help other newcomers with understanding the concepts when feeling confused with them.

Today I’ll show how I approached and solved the NAND Challenge.

We are given two circuits to make a NAND gate: the first one, default on, is only on when the current is zero and the second one, default off, is only on when the current is one. Both circuits have an input, an output, and a current. The current determines if the circuit will be on or off. If so, the input will be given to the output. Otherwise, the output is zero regardless of the value of the input.

In order to make a NAND gate, we need to make an AND gate and a NOT gate.

Build AND Gate

The AND gate’s truth table is:

Input A will be the current and input B will be the input for the circuit. Firstly, we need to determine which circuit to use. Since an AND gate only outputs 1 when both A and B are 1, we need the current to be 1 for the output to receive the input. Therefore, the circuit we will use is the default off circuit.

Note: We know that this is an AND gate because the truth table on the left is the truth table for a NAND gate and all four rows have an X.

Add NOT Gate

The NOT gate’s truth table is:

For this gate, we first need to determine whether the output for the AND gate should go to the current or the input of the circuit. If the current always remains the same, then the output will either always be 0 or whatever the input is, which is not what we want. Thus, the current will be given the output of the AND gate.

Next, we need to figure out what the input will be. If the input is always 0, then the output will always be 0 regardless of the current. Accordingly, the input will always be 1.

Finally, we will figure out what type of circuit we should use. When the current is 0, the circuit should return 1. Otherwise, it will return 0. From the above description of the circuits given in the first paragraph, we are positive that the circuit is the default on circuit.