In order to get familiar with Makerchip platform and TL-Verilog, a pipelined Pythagorean example is given as a tutorial. The tutorial is very helpful, however, reading waveform can be a bit challenging especially when pipelining and the valid signal are combined together. Please read through the “VALIDITY TUTORIAL” from the “Tutorials” page.

Pipelining is an optimization strategy that involves executing parts of different tasks simultaneously. Imagine a program with three different sections. Each section takes the same amount of time to run. In the first cycle, the first part of the first task will receive its input and output it to the second part. In the second cycle, the second part of the first task will perform its job. However, the first part of the second task will also run at the same time. Then, in the third cycle, the third part of the first task will run and output the result. At the same time, the second part of the second task and the first part of the third task will also run. This allows the entire program to run much faster than iterating through each task individually.

The valid signal is composed of two random bits (for the Pythagorean example). This signal will determine if the program will run through a task with a ¼ chance of doing so. The picture below shows that when the valid signal is true (the line is green) the task runs and the numbers are highlighted. When it’s false (the line is blue) the numbers are grayed out. 

However, you may be wondering why the numbers directly above the green line, unless there is a green line before it, are grayed out. This is because of the aforementioned pipelining strategy. The valid signal and the first part of the task aren’t run in the same section. The valid signal is determined first before being given to the first part. Because of this, the task that will actually run is the task in the cycle directly afterwards.

In the above waveform, I highlighted three tasks: task 1 (yellow), task 2 (red), and task 3 (blue). The solid yellow marks the valid cycle that is followed by pipeline 1 (@1) of task 1. The solid red marks the valid cycle that is followed by pipeline 1 of task 2. The solid blue marks the valid cycle that is followed by pipeline 1 of task 3. Note: the validity cycle only marks the initiating of pipeline 1 of a task and won’t prevent running of further pipelines for the same task even if the validity cycle is done.