The fibonacci sequence is a sequence of numbers where the first two terms are both 1 and the next terms are the sum of the two previous terms. In order to output the terms of this sequence using TL-Verilog, you need to be able to access previous cycles of numbers. This is where the “>>” operation comes in. 

In TL-Verilog, >> indicates that you want the value of some previous cycle of a variable. The storage of values from previous cycle is realized through the “D Flip-Flop“, the square block with a small triangle in it. For example, if you set something equal to >>3$num, the value will be the value of num three cycles before. With this operation in mind, it seems fairly trivial to come up with the code for the fibonacci sequence. The line of code

$num[31:0] = >>1$num + >>2$num;

seems to be enough. What this line means is that the variable “num”s value is equal to the previous cycle’s value and the value two cycles earlier. However, the only issue with this is that for the first cycle, there is no previous cycle. The way to bypass this issue is through a reset variable and a multiplexer.

The reset variable has value 1 for the first couple cycles. Afterwards, the value becomes 0. This works well with a multiplexer, since you could define num as some value when reset is 1 and then start computing the rest of the terms when reset is 0. Since you want the first two terms to be 1, the lines of code will be the following:

$num[31:0] = $reset ? 1 : (>>1$num + >>2$num);

The waveform shows reset lasts more than two cycles (yellow highlighted), enough to get two previous cycles of consecutive “1” as the initial fibonacci sequence.